1. Field of the Invention
The present invention relates to a data reading circuit for a semiconductor memory device, and in particular to an improved data reading circuit for a semiconductor memory device which is capable of enhancing the characteristic of a high speed latching sense amplifier by using both a latching sense amplifier and a current mirror type sense amplifier and by which the data reading circuit is more stably operated with respect to input noise.
2. Description of the Conventional Art
FIG. 1 illustrates a conventional data reading circuit for a semiconductor memory device, which includes a decoder 1 receiving and decoding applied address signals ADD0 and ADD1, a memory cell array 2 accessed by the signals CA0 and CA1 outputted from the decoder 1, a controller 3 receiving address transition detection signals ATD0 and ATD1 generated upon detecting transitions of the address signals ADD0 and ADD1, and a latching sense amplifier 4 receiving signals EQ and EN outputted from the controller 3 and data DATA and DATAB outputted from the memory cell array 2 and outputting an output signal S0.
The operation of the conventional data reading circuit for a semiconductor memory device will now be explained with reference to the accompanying drawings.
First, as shown in FIG. 2, when the address signal ADD0 is inputted to the decoder 1, it is decoded thereby and a corresponding cell access signal CA0 is generated and is outputted to the memory cell array 2.
The data signal stored in memory cell array 2 is thereby read out in response to the cell access signal CA0 and is applied to the latching sense amplifier 4.
The controller 3 receives the address transition detection signal ATD0 which is generated upon the transition of the address signal ADD0 and outputs a sense amplifier enable signal EN and a sense amplifier equalization signal EQ, respectively.
The latching sense amplifier 4 receives the sense amplifier control signals EN and EQ from the controller 3 for being equalized and enabled in accordance therewith, and receives the data signals DATA and DATAB and outputs an output signal S0.
In the conventional data reading circuit for a semiconductor memory device, the latching sense amplifier 4 is used for increasing the reliability of the data reading operation. However, as shown in FIG. 3, if a short noise pulse signal masquerading as an address signal ADD1 is inputted into the chip, the cell access signal CA1 inadvertently is generated due to the noise signal, so that an incorrect cell may be accessed. Therefore, even when the cell access signal CA0 is inputted, the corresponding data signal may not be selected. Namely, an incorrect cell data may be carried on a bit line, or the equalization may be terminated by the cell amplifier equalization signal EQ before a predetermined data is substantially carried on the bit line.
In addition, when the latching sense amplifier 4 is enabled by the sense amplifier enable signal EN, since the latching sense amplifier 4 latches an incorrect data, even when the correct data is then inputted to the latch sense amplifier 4 later, it is impossible to output the correct data again. Namely, the incorrect data is continuously outputted, thus causing a malfunction of the memory device.